1. Technical Field
The present invention relates generally to semiconductor technology and more specifically to semiconductor research and development.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from computers and radios to televisions.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each worth hundreds or thousands of dollars.
The ideal would be to have every one of the integrated circuits on a wafer functional and within specifications, but because of the sheer numbers of processes and minute variations in the processes, this rarely occurs. xe2x80x9cYieldxe2x80x9d is the measure of how many xe2x80x9cgoodxe2x80x9d integrated circuits there are on a wafer divided by the total number of integrated circuits formed on the wafer divided by the maximum number of possible good integrated circuits on the wafer. A 100% yield is extremely difficult to obtain because minor variations, due to such factors as timing, temperature, and materials, substantially affect a process. Further, one process often affects a number of other processes, often in unpredictable ways.
In a manufacturing environment, the primary purpose of experimentation is to increase the yield. Experiments are performed in-line and at the end of the production line with both production wafers and experimental wafers. However, yield enhancement methodologies in the manufacturing environment produce an abundance of very detailed data for a large number of wafers on processes subject only to minor variations. Major variations in the processes are not possible because of the time and cost of using production equipment and production wafers. Setup times for equipment and processing time can range from weeks to months, and processed wafers can each contain hundreds of thousands of dollars worth of integrated circuits.
The learning cycle for the improvement of systems and processes requires coming up with an idea, formulating a test(s) of the idea, testing the idea to obtain data, studying the data to determine the correctness of the idea, and developing new ideas based on the correctness of the first idea. The faster the correctness of ideas can be determined, the faster new ideas can be developed. Unfortunately, the manufacturing environment provides a slow learning cycle because of manufacturing time and cost.
Recently, the great increase in the complexity of integrated circuit manufacturing processes and the decrease in time between new product conception and market introduction have both created the need for speeding up the learning cycle.
This has been accomplished in part by the unique development of the integrated circuit research and development environment. In this environment, the learning cycle has been greatly speeded up and innovative techniques have been developed that have been extrapolated to high volume manufacturing facilities.
To speed up the learning cycle, processes are speeded up and major variations are made to many processes, but only a few wafers are processed to reduce cost. The research and development environment has resulted in the generation of tremendous amounts of data and analysis for all the different processes and variations. This, in turn, has required a large number of engineers to do the analysis. With more data, the answer always has been to hire more engineers.
However, this is not a solution for major problems.
The problems include, but are not limited to, the need to visualize the spatial dependency of detailed semiconductor device characterization data.
The problems include, but are not limited to, unlinked queries for data visualization.
The problems include, but are not limited to, classification of in-line defects.
The problems include, but are not limited to, difficulties with in-line defect kill rate prediction and image recognition.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
The present invention provides a method for processing tester information. Data is collected for all dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data is graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer. This provides a methodology and output format to display die level and wafer level data simultaneously showing spatial dependencies that cannot be identified by other means.
Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.